Background calibration of aperture center errors in analog to digital converters

ABSTRACT

A method of background calibration of aperture center errors in a data communication system is provided. In an implementation, in response to detection of a low sampler output (“0”) in between two high sampler outputs (“1”), the method includes: determining a direction of an ADC output signal at the time of the detected low output; and adjusting timing at a selected sampler based on the determined signal direction. In an example implementation, the method includes watching for bubbles in the thermometer code output, and estimating the first derivative of the signal at the time of the bubble, then estimating the sign of the errors. In an example implementation, the errors are used in a control loop to reduce the aperture center error.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. patent applicationSer. No. 13/766,948 filed on Feb. 14, 2013, which is related to commonlyassigned U.S. patent application Ser. No. 13/766,855 filed on Feb. 14,2013 entitled “Background Calibration of Threshold Errors in Analog toDigital Converters,” both of which are incorporated herein by referencein their entirety.

FIELD

The present disclosure relates generally to analog to digital converters(ADCs) that are used in data communications, for exampleserializer/deserializer (SerDes) and optical transceivers. Moreparticularly, the present disclosure relates to aperture centercalibration in such data communications.

BACKGROUND

A flash ADC comprises a set of comparators, each with a differentthreshold. For ADC comparators, the thresholds are normally linearlyspaced with respect to each other, although this constraint is notnecessary. An important constraint is that the thresholds be known tothe downstream digital signal processor (DSP). For a bank of comparatorsarranged such that they are evenly and linearly spaced, such that thethreshold voltage between any two thresholds is the same, the quality ofthe data conversion depends on the linearity of that spacing. An exampleimplementation with 16 threshold levels would provide a data convertorof 4 bits (since 2⁴=16). This would require 16 evenly spaced thresholds.If the thresholds are not evenly spaced, the effective resolution of ADCis lower than 16.

Often, the comparator set is preceded by a single sample and holdcircuit, which samples the input signal and holds its output while thecomparators make the comparison to their respective thresholds.

The “hold” cycle of a sample and hold circuit is imperfect in the sensethat the output signal may still be changing at the input to thecomparators, particularly for very high speed flash ADCs. Other flashADCs forego the sample and hold, which virtually guarantees that thesignal will be changing while the comparators are making their decision.

The comparators in an ADC are normally clocked; such comparators arealso referred to herein as “samplers”. Ideally each sampler samples theinput signal at the same instant. The samplers are analog circuits whoseideal input-output relationship can be described as:output_(k)(iT)=sign(input(iT)−threshold_(k))  Equation 1where i is the sample index (the ith sample), and T is the samplingperiod and k is the kth comparator in a set of comparators.

However the real-life, or non-ideal, behavior of the sampler and sampleand hold circuit introduces a threshold offset, and a sampling timeoffset, thereby distorting the kth sampler as shown below.output_(k)(iT)=sign(input(iT+apertureError_(k))−threshold_(k)+offset_(k))  Equation2where apertureError_(k) is the timing error of the kth sampler. Theaperture timing error can in general be different for each sampler. Inthe present disclosure, the “common mode” aperture error is the averageof all the individual aperture errors, and the “differential mode”aperture error is the difference between any two aperture samplingtimes.

It is desirable to remove the effect of apertureError_(k) and offset_(k)with calibration. The present disclosure addresses apertureError_(k).

There are two categories of calibration: foreground and background.Foreground calibration refers to a procedure performed in such a way asto disrupt the normal signal flow through the ADC, often by temporarilyremoving the normal ADC input signal and introducing a known calibrationinput signal. By doing so, during foreground calibration the system inwhich the ADC is performing the data conversion is not able to processthe normal input signal. This disruption can sometimes be tolerated atcertain times in the life cycle of the system with the ADC, perhaps fora brief time at power up.

Background calibration refers to a calibration procedure in which thenormal signal flow of the system with the ADC is not disrupted in anyway; the system can continue to process data from the ADC and expect theconversion performance to be within specified bounds, and expect thatthe normal input signal is being converted.

In an implementation, a flash ADC is a single set of comparators whichall sample the input signal at the same instant. Such an ADCimplementation is shown in FIG. 1A. Very high speed flash ADCs oftenemploy “time-interleaving” in which a total flash ADC comprises severaltime-interleaved sub-ADCs, as shown in FIG. 1B which illustrates atwo-phase interleaved flash. In an example using time-interleavedsub-ADCs, as shown in FIG. 1B, each sub-ADC comprises a set ofcomparators running off a different phase of a lower speed clock.Time-interleaving allows samplers to run off of a slower clock whilemaintaining the higher speed net sampling frequency.

Recall the input-output relationship of an analog sampler:output_(k)(iT)=sign(input(iT+apertureError_(k))−threshold_(k)+offset_(k))  Equation3

Estimating and calibrating the offsetk is the subject of the relatedcommonly assigned U.S. patent application Ser. No. 13/766,855 (AttorneyRef. PAT 7079-2) entitled “Background Calibration of Threshold Errors inAnalog to Digital Converters”.

It is desirable to estimate and reduce apertureError_(k).

FIG. 2 illustrates a grid 10 as a representation of a time-interleavedflash ADC, in which time is on the horizontal axis and thresholdamplitude is on the vertical axis. Ideally, voltage is spaced linearlyor vertically, as shown by the ideal times and amplitudes 12 in FIG. 2.However, since it is also desirable to have the comparators spacedlinearly in time (to achieve time-interleaving), which is shownhorizontally, the threshold voltage would be interleaved. The horizontalspacing stands for when the sample occurs, which is also shown in FIG.2.

FIG. 3 illustrates the impact of threshold errors due to sampleroffsets. The measured values 14 include threshold errors, and move upand down with respect to the ideal values 12; the measured values 14 arenot evenly spaced, and require correction.

FIG. 4 illustrates the impact of both threshold and aperture timingerrors by illustrating measured values 16 which include threshold andaperture center errors. The aperture timing errors are represented inthe values 16 by a shift to the left and right with respect to theideal. For a given column of samplers, it is desirable that all samplerssample at the same time. Because the input signal could be changing, ifsamples are taken too early or too late with respect to the ideal value,this can result in not properly representing the analog signal at agiven time, which is undesirable.

As shown in FIG. 5, a problem arises when an analog signal 18 passesbetween the measured timing instants, or measured values, 16 of twosamplers. FIG. 5 illustrates that there could be a problem if thesamples are not sampling at the same instant, which is illustrated aslined up horizontally. If the analog signal happens to slip in betweentwo of the measured values 16 as shown, this results in an error asshown in FIG. 6.

FIG. 6 illustrates the output of the individual samplers in the scenarioof FIG. 5, showing occurrence of a “sparkle code” or “bubble”, which isdefined as a 0 between two 1s. In FIG. 6, ideal values 20 are the outputof the ideal sampler, while measured values 22 are the measured outputof a real sampler, including amplitude and aperture timing errors. Thesampler output should be a 1 if the analog signal is above thethreshold, and the output should be 0 if the analog signal is below thethreshold.

In FIG. 6, the ideal sampler output values at samplers 24 and 26 are 1.The ideal output value at sampler 28 is 0, since the analog signal 18 isbelow the ideal threshold 12. This indicates that, based on idealsampler outputs 20, the analog signal 18 crosses the threshold betweensamplers 26 and 28. When samplers are horizontally perfectly timed, theobserved output is always a set of 1s at the bottom and a set of 0s atthe top.

In FIG. 6, the measured sampler value at sampler 24 is a 1. At sampler26, since the measured value 16 is offset “earlier” in time with respectto the ideal value 12, the threshold output is 0, even though it shouldideally have been 1. At sampler 28, since the measured value 16 isoffset “later” in time with respect to the ideal value 12, the thresholdoutput is 1, even though it should ideally have been 0. At thesubsequent samplers in FIG. 6, the ideal and real outputs are the same.

As illustrated in FIG. 6, sampler outputs with aperture and timingerrors can produce an error called a bubble code or a sparkle code,which is a 0 observed in between two 1 s at the output. In such cases,there is some confusion based on the output.

After the occurrence of bubbles has been identified, there are someknown approaches regarding what to do about the bubble. In one approach,the two comparators are identified between which the analog signalfalls, such as observing when the comparator goes from a 1 to 0.However, in the example of FIGS. 5 and 6, since the transition from a 1to 0 is a gentle one, such an approach would result in an incorrect orerroneous determination. Also, if there is more than one transition from1s to 0s, a decision must be made as to which transition is the “proper”transition.

Another approach is to add up the number of 1s, which then provides anidentification of the comparator above which the analog signal above wasobserved to make the transition. However, even in this case, this isjust an estimate.

In these known approaches, bubbles are dealt with by making a choice;but, at any time, the choices will sometimes be right and sometimes bewrong.

It is desirable to provide an alternative approach to correctingaperture center errors, which reduces or eliminates the occurrences ofbubbles.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure will now be described, by way ofexample only, with reference to the attached Figures.

FIGS. 1A and 1B illustrate example comparator arrangements innon-time-interleaved and time-interleaved flash ADCs, respectively.

FIG. 2 illustrates representation of a time-interleaved flash ADC.

FIG. 3 illustrates the impact of threshold errors due to sampleroffsets.

FIG. 4 illustrates the impact of both threshold and aperture timingerrors.

FIG. 5 illustrates an analog signal passing between the timing instantsof two samplers.

FIG. 6 illustrates the output of the individual samplers in the scenarioof FIG. 5, showing occurrence of a “bubble”.

FIG. 7 illustrates detection and correction of negative timing erroraccording to an embodiment of the present disclosure.

FIG. 8 illustrates detection and correction of a positive timing erroraccording to an embodiment of the present disclosure.

FIG. 9 is a flowchart illustrating a method of background calibrationerror of aperture center errors in a data communication system accordingto an embodiment of the present disclosure.

FIG. 10 is a block diagram illustrating a system for backgroundcalibration of aperture timing errors in a data communication systemincluding an ADC according to an embodiment of the present disclosure.

FIG. 11 is a graph illustrating a comparison of histograms of aperturetiming error before and after using a method according to an embodimentof the present disclosure.

FIG. 12 is a bar graph illustrating normal ADC output timing with andwithout aperture timing errors for each ADC output level.

DETAILED DESCRIPTION

Generally, the present disclosure provides a method of backgroundcalibration of aperture center errors in a data communication system. Inan implementation, in response to detection of a low sampler output(“0”) in between two high sampler outputs (“1”), the method includes:estimating or calculating a signal derivative of an ADC output signal atthe time of the detected low output; and adjusting timing at a selectedsampler based on the estimated or calculated signal derivative. In anexample implementation, the method includes watching for bubbles in thethermometer code output, and estimating the first derivative of thesignal at the time of the bubble, then estimating the sign of theerrors. In an example implementation, the errors are used in a controlloop to reduce the aperture center error.

In an example embodiment, the bubbles are removed rather than trying tocompensate for their occurrence. In an example embodiment, aperturecenter errors are removed in the background, in order to remove theoccurrence of “bubbles”.

In an embodiment, the present disclosure provides a method of backgroundcalibration of aperture timing errors in a data communication systemincluding an analog to digital converter (ADC) having a plurality ofsamplers, comprising: in response to detection of a low sampler output(“0”) in between two high sampler outputs (“1”), the low and highsampler outputs being at the same sampler in the plurality of samplers:calculating a signal derivative of an ADC output signal at the time ofthe detected low output; and adjusting timing at a selected samplerbased on the calculated signal derivative.

In an example embodiment, calculating the signal derivative comprisesdetecting a negative timing error; and adjusting the timing at theselected sampler comprises moving the timing later in time such thatsampler timing occurs later than before the adjustment to compensate forthe detected negative timing error.

In an example embodiment, calculating the signal derivative comprisesdetecting a positive timing error; and adjusting the timing at theselected sampler comprises moving the timing earlier in time such thatsampler timing occurs earlier than before the adjustment to compensatefor the detected positive timing error.

In an example embodiment, calculating the signal derivative comprisescomparing an ADC output level at a current time sample with an ADCoutput level at a previous time sample.

In an example embodiment, the method further comprises: detecting thelow sampler output in between the two high sampler outputs based onobservation of a thermometer encoded sampler output.

In an example embodiment, adjusting the timing, or accounting for atiming error, at the selected sampler comprises a DSP interpolation toresample a waveform to provide equally timing spaced output samples. Inan example embodiment, the DSP interpolation is performed using a map ofADC output level values and aperture timing error estimations.

In an example embodiment using DSP interpolation, the method furthercomprises: counting a number of aperture error events for each of theplurality of samplers; converting the aperture error count to anaperture error value in real time units; building a map of ADC outputlevels and their associated aperture timing error; and resampling, usingthe map and in the digital domain, a waveform corresponding to the ADCoutput signal using the real timing locations for each ADC output value.

In an embodiment, the present disclosure provides a computer-readablestorage device storing statements and instructions for execution by aprocessor to perform a method of background calibration of aperturetiming errors in a data communication system including an analog todigital converter (ADC) having a plurality of samplers, comprising: inresponse to detection of a low sampler output (“0”) in between two highsampler outputs (“1”), the low and high sampler outputs being at thesame sampler in the plurality of samplers: calculating a signalderivative of an ADC output signal at the time of the detected lowoutput; and adjusting timing at a selected sampler based on thecalculated signal derivative.

In an embodiment, the present disclosure provides a system forbackground calibration of aperture timing errors in a data communicationsystem including an analog to digital converter (ADC) having a pluralityof samplers, comprising: a signal processor configured to, in responseto detection of a low sampler output (“0”) in between two high sampleroutputs (“1”), the low and high sampler outputs being at the samesampler in the plurality of samplers, calculate a signal derivative ofan ADC output signal at the time of the detected low output; and atiming adjustment circuit configured to adjust timing at a selectedsampler based on the calculated signal derivative.

In an example embodiment: the signal processor detects a negative timingerror; and the timing adjustment circuit is configured to move thetiming later in time such that sampler timing occurs later than beforethe adjustment to compensate for the detected negative timing error. Inan example embodiment, the negative timing error is detected as:(Bubble[i]) AND (SignalDerivative[i]>0), where Bubble is defined as alow sampler output (“0”) below a high sampler output (“1”), and whereinSignalDerivative[i]=ADCoutput[i]−ADCoutput[i−1].

In an example embodiment: the signal processor is configured to detect apositive timing error; and the timing adjustment circuit is configuredto move the timing earlier in time such that sampler timing occursearlier than before the adjustment to compensate for the detectedpositive timing error. In an example embodiment, the positive timingerror is detected as: (Bubble[i]) AND (SignalDerivative[i]<0), whereBubble is defined as a low sampler output (“0”) below a high sampleroutput (“1”), and whereinSignalDerivative[i]=ADCoutput[i]−ADCoutput[i−1].

In an example embodiment, the signal processor is configured to comparean ADC output level at a current time sample with an ADC output level ata previous time sample. In another example embodiment, the signalprocessor is configured to detect the low sampler output in between thetwo high sampler outputs based on observation of a thermometer encodedsampler output.

In an example embodiment, the system further includes a digital signalprocessor (DSP), the signal processor and the timing adjustment circuitbeing integral with the DSP, the DSP being configured to adjust thetiming at the selected sampler using DSP interpolation to resample awaveform to provide equally timing spaced output samples. In an exampleembodiment, the DSP is configured to perform the DSP interpolation usinga map of ADC output level values and aperture timing error estimations.In an example embodiment, the DSP is configured to: count a number ofaperture error events for each of the plurality of samplers; convert theaperture error count to an aperture error value in real time units;build a map of ADC output levels and their associated aperture timingerror; and resample, using the map and in the digital domain, a waveformcorresponding to the ADC output signal using the real timing locationsfor each ADC output value.

Other aspects and features of the present disclosure will becomeapparent to those ordinarily skilled in the art upon review of thefollowing description of specific embodiments in conjunction with theaccompanying figures.

A method of background calibration of comparator aperture timing errorsin a flash ADC according to an embodiment of the present disclosure willnow be described.

A negative timing error is detected as(Bubble[i]) AND (SignalDerivative[i]>0)  Equation 4where Bubble is defined as a 0 “below” a 1. Note that “below” means thesampler has a relatively lower threshold. The signal derivative isdetected by comparing the current time sample to the previous timesample, orSignalDerivative[i]=ADCoutput[i]−ADCoutput[i−1]  Equation 5

A “thermometer code” can be used to represent outputs of an ADC. Using athermometer code of N bits, there is one bit used for each discretepossible value. For example, an 8-bit code can be used to represent thenumbers 0-8, where: 0 is represented by 00000000; 3 is represented by11100000; 5 is represented by 11111000; and 8 is represented by11111111. A “bubble” is easily identified as an error in a thermometercode output, since a thermometer code by definition has at most onetransition from 1s to 0s.

It is worthwhile to distinguish between: the total ADC output, whichrepresents the magnitude of the input signal and where the signalderivative is detected; and the sampler set thermometer encoded output,where the bubbles are detected. Note that the ADC output and the samplerthermometer encoded output can be the same, but used differently.

FIGS. 7 and 8 illustrate the detection and correction of different typesof timing errors according to an embodiment of the present disclosure.Because the sampler output is digital, it is possible to observe theoutput and simply look for the presence of the bubble. Embodiments ofthe present disclosure look for two kinds of bubbles, which are shown inFIGS. 7 and 8. The first kind of bubble, shown in FIG. 7, occurs whenone presumes that the analog signal 18 is travelling in the upwarddirection in time, and therefore there is a movement from a low value toa higher value. Upon detection of a bubble, and knowing that the analogsignal 18 is travelling in the upward direction, a method according toan embodiment of the present disclosure pushes the error to the right.This is shown by the arrow 50 in FIG. 7, which represents the directionin which a method according to an embodiment of the present disclosuremoves the timing of the bottom sampler.

In FIG. 7, the horizontal dimension is time and the vertical dimensionis amplitude. When the analog signal 18 appears as shown in FIG. 7,between the measured values 16 which represent the amplitude andaperture timing of two consecutive comparators, a bubble conditionoccurs since a 0 is below a 1. In this case, the method according to anembodiment of the present disclosure detects a negative timing error andmoves the timing of the lower sampler forward in time by some smallamount.

A positive timing error is detected as(Bubble[i]) AND (SignalDerivative[i]<0)  Equation 6

FIG. 8 illustrates detection and correction of a positive timing erroraccording to an embodiment of the present disclosure. In FIG. 8, thehorizontal dimension is time and the vertical dimension is amplitude.When the analog signal 18 appears as shown between the measured values16, a bubble condition occurs since a 0 is below a 1. In this case, themethod according to an embodiment of the present disclosure detects apositive timing error and will move the timing of the lower samplerearlier in time by a small amount. This is shown by the arrow 60 in FIG.8, which represents the direction in which a method according to anembodiment of the present disclosure moves the timing of the bottomsampler.

According to embodiments of the present disclosure, when the directionof the signal is known, the timing of the comparator gate is moved basedon the detected direction of the signal, which can be calculated basedon a signal derivative. Therefore, for a detected bubble, it isdesirable to know if the 0 needs to be moved to the right or to theleft. In FIG. 7, it is desirable to move the comparator that gave a 0output to the right, and in FIG. 8 it is desirable to move it to theleft, to correct the aperture timing errors in the background.

FIG. 9 is a flowchart illustrating a method 100 of backgroundcalibration error of aperture center errors in a data communicationsystem according to an embodiment of the present disclosure. The methodincludes estimating or calculating a signal derivative of an ADC outputsignal at the time of the detected low output (120); and adjustingtiming at a selected sampler based on the estimated or calculated signalderivative (130). The calculating is performed in response to detectionof a low sampler output (“0”) in between two high sampler outputs (“1”),the low and high sampler outputs being at the same sampler in theplurality of samplers. In an embodiment, the method includes optionalstep 110 of detecting the low sampler output in between the two highsampler outputs, for example based on observation of a thermometerencoded sampler output.

In an embodiment, the step 130 comprises moving the timing earlier/laterin time based on detection of negative/positive timing error (132), inwhich case the actual timing of a sampler is moved, for example byadjusting the timing of the sampler's clock. In an alternativeembodiment, the step 130 includes performing DSP interpolation toresample a waveform to provide equally timing spaced output samples, forexample based on a map of ADC output level values and aperture timingerror estimations (134), which is effectively changing the timing in thedigital domain. In an example embodiment in which step 134 is performed,the analog timing of the sampler is left alone, but the DSP interpolatesthe output waveform such that it computes what the signal is at theideal sampler clock time. In example embodiments, either step 132 orstep 134 is performed, but they are not performed together.

In an example embodiment, calculating the signal derivative (120)comprises comparing an ADC output level at a current time sample with anADC output level at a previous time sample (122).

In an example embodiment, calculating the signal derivative (120)comprises detecting a negative timing error (124). In such an exampleembodiment, adjusting the timing at the selected sampler (130) comprisesmoving the timing later in time such that sampler timing occurs laterthan before the adjustment to compensate for the detected negativetiming error (132).

In another example embodiment, calculating the signal derivative (120)comprises detecting a positive timing error (124). In such an exampleembodiment, adjusting the timing at the selected sampler (130) comprisesmoving the timing earlier in time such that sampler timing occursearlier than before the adjustment to compensate for the detectedpositive timing error (132).

In an example embodiment, adjusting the timing at the selected sampler(130) comprises a digital signal processor (DSP) interpolation toresample a waveform to provide equally timing spaced output samples(134). In an example embodiment, the DSP interpolation is performedusing a map of ADC output level values and aperture timing errorestimations.

In an example embodiment, the DSP method further comprises: counting anumber of aperture error events for each of the plurality of samplers;converting the aperture error count to an aperture error value in realtime units; building a map of ADC output levels and their associatedaperture timing error; and resampling, using the map and in the digitaldomain, a waveform corresponding to the ADC output signal using the realtiming locations for each ADC output value. Such an example embodimentwill be discussed in further detail below. This method is only used forthe DSP method case, when step 134 is performed instead of step 132.

FIG. 10 is a block diagram illustrating a system 200 for backgroundcalibration of aperture timing errors in a data communication systemincluding an ADC 210 according to an embodiment of the presentdisclosure. The system includes a signal processor 220, configured toperform step 120 of FIG. 9, and in example embodiments to performrelated steps and sub-steps as described an illustrated herein. Thesystem also includes a timing adjustment circuit 230, configured toperform step 130, and in example embodiments to perform related stepsand sub-steps as described and illustrated herein. In an embodiment, thesystem further includes a DSP 240 configured to perform step 134, and inexample embodiments to perform related steps and sub-steps as describedand illustrated herein. In an example embodiment, the DSP 240 comprisesthe signal processor 220 and the timing adjustment circuit 230;alternatively, the signal processor 220 and the timing adjustmentcircuit 230 are integral with the DSP.

FIG. 11 is a graph 250 illustrating a comparison of histograms ofaperture timing error before and after using a method according to anembodiment of the present disclosure. FIG. 11 illustrates an example inwhich the aperture timing error histogram 252 before using a methodaccording to an embodiment of the present disclosure shows about 12occurrences of an aperture error of zero, and many occurrences ofaperture errors between −4 and +4 ps. In contrast, the aperture timingerror histogram 254 after using a method according to an embodiment ofthe present disclosure shows over 20 occurrences of an aperture error ofzero, and a significant decrease of errors between −4 and +4 ps,particularly in the range of −2 to +2 ps.

A method according to an embodiment of the present disclosure asdescribed above shows the aperture timing of the samplers being moved asthe method detects bubbles, to force the aperture times to all occur atthe same instant. This is essentially an analog technique.

In another embodiment, rather than move the analog sampler aperturetimes, DSP interpolation is performed, such as described generally withrespect to step 134 in FIG. 9. To do this, it is recognized thataperture timing errors mean that each possible ADC output value actuallyoccurs at a time other than the ideal sample time.

FIG. 12 is a bar graph illustrating normal ADC output timing with andwithout aperture timing errors for each ADC output level. For the idealoutputs, without errors, each sample occurs at an integer multiple ofthe sampling period. The bars 264 with the round ends show the idealsampling instant, and the bars 152 with the square ends show the actual,or measured, timing instant. Each ADC output level includes a pair ofbars 152 and 154. In the example embodiment of FIG. 12, for each ADCoutput level, the timing error is defined as the difference between thelocation of the pair of ideal and actual sampling instant bars 152 and154.

With the timing error for each ADC output level estimated as describedabove, this information can be used to interpolate, or digitallyre-sample the waveform back to the desired timing instants.

A method according to an embodiment of the present disclosure involvingDSP interpolation can be described as follows:

1. Detect positive and negative aperture errors as described above,except do not move the analog sampler aperture timing; instead, countthe number of aperture error events for each sampler. So, for each ADCoutput code, an associated aperture error count, or C(ADCcode), isobtained or calculated.

2. Multiply the C(ADCcode) counts by K(ADCcode,C(ADCcode)), to convertthe aperture error count to the aperture error value in real time units.In an embodiment, K is computed offline by simulating various apertureerror amounts and measuring the resulting number of error events for agiven time period, for each ADC output code.

3. Build a map of ADC output levels and their associated aperture timingerror, Ae.Ae(ADCcode)=K(ADCcode,C(ADCcode))*C(ADCcode)  Equation 7

4. Using this map, in the digital domain, resample the waveform usingthe real timing locations for each ADC output value.

As an illustrative example, in the Matlab programming language, thismethod could be expressed asResampledOutput=interp1(0:T:endTime+Ae(ADCoutput),ADCcodes,0:T:endTime);  Equation8where ADCoutput is the signal waveform out of the ADC, T is the idealsampling period, and ResampledOutput is the ADC output signal re-timedso that all samples occur at multiples of the ideal sampling period, or,kT.

Note that embodiments of the present disclosure do not assume thatMatlab will be used on chip; rather, Equation 8 is used to express whatinterpolation is occurring and how the on chip values will be used.

According to an embodiment of the present disclosure, knowing whetherthe signal is travelling up or down can make an important difference;however all we have is the ADC itself to indicate if the signal isincreasing or decreasing. According to an embodiment of the presentdisclosure, the signal derivative is observed across two major samples,which in an example embodiment is two of the interleaves. In an exampleembodiment, as shown in FIG. 7, only two of the comparators are chosenfor a given leaf, even though there is whole other column of comparatorsfor the signal derivatives. In an example embodiment, the last columnsignal is compared to the current column signal to determine if thesignal is travelling up or down. While it is possible that thiscomparison can give incorrect results because of the potential bubble,it is still on average providing an accurate indication of whether thesignal is going up or down, and that is described with the signalderivative.

Embodiments of the present disclosure enable lower power ADCs and/orhigher performance ADCs. The ADC is a fundamental object of signalprocessing in many communications products. Embodiments of the presentdisclosure provide a competitive advantage in power or performance, orboth.

In the preceding description, for purposes of explanation, numerousdetails are set forth in order to provide a thorough understanding ofthe embodiments. However, it will be apparent to one skilled in the artthat these specific details are not required. In other instances,well-known electrical structures and circuits are shown in block diagramform in order not to obscure the understanding. For example, specificdetails are not provided as to whether the embodiments described hereinare implemented as a software routine, hardware circuit, firmware, or acombination thereof.

Embodiments of the disclosure can be represented as a computer programproduct stored in a machine-readable medium (also referred to as acomputer-readable medium, a processor-readable medium, or a computerusable medium having a computer-readable program code embodied therein).The machine-readable medium can be any suitable tangible, non-transitorymedium, including magnetic, optical, or electrical storage mediumincluding a diskette, compact disk read only memory (CD-ROM), memorydevice (volatile or non-volatile), or similar storage mechanism. Themachine-readable medium can contain various sets of instructions, codesequences, configuration information, or other data, which, whenexecuted, cause a processor to perform steps in a method according to anembodiment of the disclosure. Those of ordinary skill in the art willappreciate that other instructions and operations necessary to implementthe described implementations can also be stored on the machine-readablemedium. The instructions stored on the machine-readable medium can beexecuted by a processor or other suitable processing device, and caninterface with circuitry to perform the described tasks.

The above-described embodiments are intended to be examples only.Alterations, modifications and variations can be effected to theparticular embodiments by those of skill in the art without departingfrom the scope, which is defined solely by the claims appended hereto.

What is claimed is:
 1. A method of background calibration of aperturetiming errors in a data communication system including an analog todigital converter (ADC) having a plurality of samplers, comprising: inresponse to detection of a low sampler output (“0”) in between two highsampler outputs (“1”), the low and high sampler outputs being at thesame sampler in the plurality of samplers: determining a direction of anADC output signal at the time of the detected low output; and adjustingtiming at a selected sampler based on the determined signal direction.2. The method of claim 1 wherein: determining the signal directioncomprises detecting a negative timing error; and adjusting the timing atthe selected sampler comprises moving the timing later in time such thatsampler timing occurs later than before the adjustment to compensate forthe detected negative timing error.
 3. The method of claim 2 wherein thenegative timing error is detected as:(Bubble[i]) AND (SignalDerivative[i]>0); where Bubble is defined as alow sampler output (“0”) below a high sampler output (“1”), and whereinSignalDerivative[i]=ADCoutput[i]−ADCoutput[i−1].
 4. The method of claim1 wherein: determining the signal direction comprises detecting apositive timing error; and adjusting the timing at the selected samplercomprises moving the timing earlier in time such that sampler timingoccurs earlier than before the adjustment to compensate for the detectedpositive timing error.
 5. The method of claim 4 wherein the positivetiming error is detected as:(Bubble[i]) AND (SignalDerivative[i]<0); where Bubble is defined as alow sampler output (“0”) below a high sampler output (“1”), and whereinSignalDerivative[i]=ADCoutput[i]−ADCoutput[i−1].
 6. The method of claim1 wherein: determining the signal direction comprises comparing an ADCoutput level at a current time sample with an ADC output level at aprevious time sample.
 7. The method of claim 1 further comprising:detecting the low sampler output in between the two high sampler outputsbased on observation of a thermometer encoded sampler output.
 8. Themethod of claim 1 wherein: adjusting the timing at the selected samplercomprises a digital signal processor (DSP) interpolation to resample awaveform to provide equally timing spaced output samples.
 9. The methodof claim 6 wherein the DSP interpolation is performed using a map of ADCoutput level values and aperture timing error estimations.
 10. Themethod of claim 6 further comprising: counting a number of apertureerror events for each of the plurality of samplers; converting theaperture error count to an aperture error value in real time units;building a map of ADC output levels and their associated aperture timingerror; and resampling, using the map and in the digital domain, awaveform corresponding to the ADC output signal using the real timinglocations for each ADC output value.
 11. A computer-readable storagedevice storing statements and instructions for execution by a processorto perform a method of background calibration of aperture timing errorsin a data communication system including an analog to digital converter(ADC) having a plurality of samplers, comprising: in response todetection of a low sampler output (“0”) in between two high sampleroutputs (“1”), the low and high sampler outputs being at the samesampler in the plurality of samplers: determining a signal direction ofan ADC output signal at the time of the detected low output; andadjusting timing at a selected sampler based on the determined signaldirection.
 12. A system for background calibration of aperture timingerrors in a data communication system including an analog to digitalconverter (ADC) having a plurality of samplers, comprising: a signalprocessor configured to, in response to detection of a low sampleroutput (“0”) in between two high sampler outputs (“1”), the low and highsampler outputs being at the same sampler in the plurality of samplers,determine a signal direction of an ADC output signal at the time of thedetected low output; and a timing adjustment circuit configured toadjust timing at a selected sampler based on the determined signaldirection.
 13. The system of claim 12 wherein: the signal processordetects a negative timing error; and the timing adjustment circuit isconfigured to move the timing later in time such that sampler timingoccurs later than before the adjustment to compensate for the detectednegative timing error.
 14. The system of claim 13 wherein the negativetiming error is detected as:(Bubble[i]) AND (SignalDerivative[i]>0); where Bubble is defined as alow sampler output (“0”) below a high sampler output (“1”), and whereinSignalDerivative[i]=ADCoutput[i]−ADCoutput[i−1].
 15. The system of claim12 wherein: the signal processor is configured to detect a positivetiming error; and the timing adjustment circuit is configured to movethe timing earlier in time such that sampler timing occurs earlier thanbefore the adjustment to compensate for the detected positive timingerror.
 16. The system of claim 15 wherein the positive timing error isdetected as:(Bubble[i]) AND (SignalDerivative[i]<0); where Bubble is defined as alow sampler output (“0”) below a high sampler output (“1”), and whereinSignalDerivative[i]=ADCoutput[i]−ADCoutput[i−1].
 17. The system of claim12 wherein: the signal processor is configured to compare an ADC outputlevel at a current time sample with an ADC output level at a previoustime sample.
 18. The system of claim 12 wherein: the signal processor isconfigured to detect the low sampler output in between the two highsampler outputs based on observation of a thermometer encoded sampleroutput.
 19. The system of claim 12 further comprising: a digital signalprocessor (DSP), the signal processor and the timing adjustment circuitbeing integral with the DSP, the DSP being configured to adjust thetiming at the selected sampler using DSP interpolation to resample awaveform to provide equally timing spaced output samples.
 20. The systemof claim 19 wherein the DSP is configured to perform the DSPinterpolation using a map of ADC output level values and aperture timingerror estimations.
 21. The system of claim 19 wherein the DSP isconfigured to: count a number of aperture error events for each of theplurality of samplers; convert the aperture error count to an apertureerror value in real time units; build a map of ADC output levels andtheir associated aperture timing error; and resample, using the map andin the digital domain, a waveform corresponding to the ADC output signalusing the real timing locations for each ADC output value.